EC has programs investigating two different types of Si-based solar cells. One utilizes thin film amorphous (a-Si) and nanocrystalline (nc-Si) technology and the other merges a-Si with wafer-based crystalline Si (c-Si) to fabricate hybrid heterojunction devices.
Thin Film Silicon Technology at IEC
The IEC has over 30 years of continuous funding in support of developing amorphous Si and thin Si solar cell processing and device design. In the 1980’s and 1990’s, IEC’s thin Si film work focused on single junction a-Si solar cells. We developed a novel Hg sensitized photo-chemical vapor deposition (photo-CVD) reaction system to deposit high quality a-Si and a-SiGe films and devices.
This lead to fabrication of the first 10% efficient single junction a-Si solar cell by a US university and very low defect a-SiGe films for tandem cells. Next, a standard plasma-CVD system was designed and built. It also allowed IEC to produce single junction devices with initial efficiencies of 10%i. Thus, the IEC is the only US university to achieve this level of NREL-confirmed efficiencies with 2 completely different growth deposition methods. The effect of textured transparent conductive oxide (TCO) such as textured SnO2 or ZnO has been subject of focused research.
We worked closely with major US manufacturers: optimizing the interconnect junction in for a-Si tandem modulesii and developing new methods to characterize the TCO/p contact in cells or modulesiii. Analysis of optical enhancement identified parasitic absorption in the textured SnO2 as the source of the unexplained optical loss in textured a-Si devices.
Figure 1 shows the concept of light trapping due to scattering from the textured TCO, and the improvement in quantum efficiency response with textured TCO compared to a smooth TCO substrate, leading to a 15% increase in photocurrent.
We also designed and installed a Hot Wire CVD (HWCVD) system in which the film growth proceeds from decomposition of SiH4 on a hot filament yielding a very different gas phase chemistry from plasma-CVD. Amorphous and nanocrystalline Si films could be deposited at very high growth rates. HWCVD Si films were used to evaluate Aluminum Induced Crystallization (AIC) to convert a-Si to crystalline Si with a goal of making thin Si solar cells. Films with large Si grain sizes were obtained but uniformity and Al contamination prevented further device fabrication. The applicability of HWCVD for deposition of SiN or other passivation layers for c-Si solar cells is being investigated.
In 2004, IEC installed a multi-chamber plasma-CVD system (Figure 2) capable of deposition over 1 square foot areas (see photo). Plasma diagnostics such as optical emission spectroscopy have been applied. Recent work has been focused on increasing the deposition rate of nc-Si films used in the bottom cell of a ‘micromorph’ a-Si/nc-Si tandem cell, which is becoming the industry standard. The effect of enhanced growth rates on crystalline fraction and initial and stabilized efficiency is being investigated. Recently, we have assisted several US companies to develop new substrate TCO materials, deposition methods, or device concepts for a-Si based solar cells.
Figure 2. Multichamber PECVD tool with load-lock entrance chamber opened.
Figure 3. Standard Si Heterojunction device (SHJ, upper left) and interdigitated all back contact device (IBC, upper right) and their merger leading to IEC’s SHJ-IBC device.
Si Heterojunctions for high efficiency front and back contacted solar cells
A new approach to the fabrication of crystalline silicon solar cells is the deposition of wide-band gap semiconductors to form a Si heterojunction (SHJ) and achieve higher efficiencies. The figure above on the left shows a typical SHJ device with deposited intrinsic and doped a-Si layers forming a heterojunction front emitter and rear contact. SHJ devices fabricated with PECVD deposited contacts and emitters use lower processing temperatures (250°C) which enables working with thinner wafers. Using the deposited a-Si doped and intrinsic layers, we have developed the SHJ approach to fabricate front junction devices with efficiencies of 18.8 % (confirmed by NREL) on textured Cz substrates.
We have also achieved open circuit voltages of 702 mV (confirmed by NREL and also on Cz substrates). Si wafer surface cleaning and a-Si intrinsic layer deposition are critical to obtaining high lifetime, VOC and FF i,ii . We are currently studying how the heterojunction device performance depends on the doping levels and intrinsic layer growth, and on wafer conductivity ( p-Si or n-Si) as relates to the heterojunction band offsets. Figure 4 shows illuminated J-V performance for 3 SHJ devices fabricated and measured at IEC, having polished p-Si (Cz) and polished or textured n-Si (FZ). The parameters are listed in Table 1.their merger leading to IEC’s SHJ-IBC device.
|Wafer||Structure||Voc (V)||Jsc (mA/cm2)||FF(%)||Eff (%)|
|300 µm FZ p (polished)||ITO/n-i-p-i-p/Al||0.637||32.1||73.7||15.1|
|150 µm FZ n (polished)||ITO/p-i-n-i-n/Al||0.687||30.6||74.7||15.7|
|150 µm Cz n (textured)||ITO/p-n-n/Al||0.595||35.8||77.3||16.4|
|Table 1. Results from three different FC-SHJ structures. Two are on polished and one on textured Si wafers. Cell area 0.56 cm2 and measured at IEC under AM1.5 simulated illumination.|
Figure 5. First published efficiency of an interdigitated back contact (IBC) solar cell using silicon heterojunction (SHJ-IBC)
Rear junction, interdigitated back contact (IBC) solar cells (as shown above in the diagram on the right) have several advantages over the more common front junction solar cell with contacts on either side Moving all the contacts to the back of the cell eliminates contact shading, leading to a high JSC. With all the contacts on the back of the cell, series resistance losses are reduced as the trade-off between series resistance and reflectance is avoided and contacts can be made far larger. Having all the contacts on the one side simplifies cell stringing during module fabrication and improves the packing factor. The reduced stress on the wafers during interconnection improves yields, especially for large thin wafers. The more uniform appearance of the PV module is desirable for architectural applications.
While the advantages of rear junctions are well known, their implementation is hindered by several design constraints, which are circumvented by amorphous silicon on crystalline silicon heterojunctions. An example of this device structure is shown as the combination of the SHJ and IBC cells above. First, since rear junction cells require diffusion lengths greater than twice the device thickness, thin wafers are attractive. Using low temperature depositions rather than high temperature diffusions decreases the thermal stress and reduces the bowing in thin wafers. Deposition temperatures are also low enough to prevent impurity indiffusion and maintain high initial lifetime of n-type substrates. Second, rear junction designs require low front surface recombination velocities, which can be provided by deposited passivation layers. Thirdly, the central challenge in rear junction solar cells, patterning the rear, is easier in silicon heterojunctions since it is much easier to mask and etch depositions than diffusions, and further isolation between p/n a-Si layers is not always necessary. IEC has publishedviii the first confirmed efficiency of such a device shown in Figure 5. We demonstrated that heterojunctions solve many of the problems with the IBC approach and achieved a high open circuit voltage of 691 mV indicating the future potential of the device structure. We have also implemented two-dimensional device modeling of a silicon heterojunction device. Another major focus of our work is optimizing the front multi-layer stack for both high transparency and low surface recombinationix.
All back contact cells are particularly suited to heterojunctions as they eliminate the costly front transparent conductive oxide (typically indium-tin-oxide) along with its absorption losses. Interestingly, with the heterojunction material on the rear, it no longer needs to be transparent and thus there is a wider flexibility in choosing heterojunction partner materials as not all wide band gap semiconductors are completely transparent.
i S. Hegedus, W. Buchanan, E. Eser, “Improving performance of superstrate p-i-n a-Si solar cells by optimization of back contacts,” Proc. 26th IEEE Photovoltaic Spec Conf (1988 Las Vegas) 129-134; also Final Report for DOE/NREL subcontract XAK-7-17609-01.
ii S. Hegedus, F Kampas, J Xi “Current transport in amorphous Si n/p junctions and their application as tunnel junctions in tandem solar cells” Appl Phys Lett 67 (1995) 813-815.
iii S Hegedus, R Kaplan, G Ganguly, G Wood “Characterization of the SnO2/p and ZnO/p contact resistance and junction properties in a-Si p-i-n solar cells and modules” Proc 28th IEEE Photovoltaic Spec Conf (Anchorage, 2000) 728-731.
iv S Hegedus, R Kaplan “Analysis of Quantum Efficiency and Optical Enhancement in a-Si p-i-n solar cells” Prog in Photovoltaics 10 (2002) 257-269.
v Ebil paper on AIC
vi U. Das, M. Burrows, M. Lu, S. Bowden, R. Birkmire, Appl Phys Lett 92 (2008) 063504
viiJ. Appel, L. Zhang, U. Das, S. Hegedus, S. Mudiganda, R Birkmire, J Rand, 35th IEEE Photovoltaic Specialist Conf (2010)
viiiM Lu, S. Bowden, U. Das, R. Birkmire, Appl Phys Lett 91 (2007) 063507
ix B Shu, U Das, O Jani, S Hegedus, R Birkmire, Proc 34th IEEE Photovoltoltaic Spec Conf (2009).